1. Field of the Invention
The present invention relates to an apparatus for testing embedded memory arrays within a microprocessor. More particularly, the invention relates to an apparatus for testing negative edge SRAM arrays not having dedicated test circuitry via scan ATPG and other memory test algorithms.
2. The Prior Art
Large RAM arrays embedded in microprocessors are typically tested via a dedicated test mode with dedicated pins. However, small RAM arrays do not include dedicated test mode capability, since such a capability would increase die size and performance overhead. Therefore, small RAM arrays and large RAM arrays must be tested separately.
Testing of microprocessor chips is typically performed sequentially in three separate stages. Typically, embedded large memory arrays are tested during a first stage. Next, during a second stage, the portion of the microprocessor chip excluding the memory arrays is tested via scan Automatic Test Pattern Generation (ATPG). The small memory arrays are normally disabled during the scan mode to avoid corruption of the RAM. Therefore, the embedded small memory arrays must be tested during a separate third stage.
Some microprocessor chips do not have full scan capability. Thus, only the outputs are scannable via scan ATPG. A need exists in the prior art for an apparatus for testing the small memory arrays during scan ATPG. Similarly, a need exists in the prior art for an apparatus for testing memory arrays that do not include dedicated test circuitry during scan ATPG. Moreover, it would be preferable to implement such a means while minimizing die size and performance overhead.